{"product_id":"vlsi-asic-design-flow-overview","title":"VLSI - ASIC Design Flow Overview","description":"\u003cp style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);box-sizing:border-box;color:rgb(65, 65, 65);font-family:sans-serif;font-size:14px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;margin:0px revert revert;orphans:2;padding:0px;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"\u003eIn this course, we will learn the complete ASIC design flow, covering the key stages required to transform a concept into a manufacturable chip. The course begins with specification, followed by architecture and RTL design, focusing on system organization and hardware implementation. We then explore functional verification and gate-level simulation to ensure design correctness. The course also covers Design for Testability (DFT), Static Timing Analysis (STA), and introduces physical design, including layout and GDS-II generation, providing a clear view of the overall VLSI design flow. \u003cbr\u003e \u003c\/p\u003e\u003cp style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);box-sizing:border-box;color:rgb(65, 65, 65);font-family:sans-serif;font-size:14px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;margin:0px revert revert;orphans:2;padding:0px;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"\u003eThis is a self-paced eLearning module with structured content, and knowledge checks. You are expected to complete all the sections to earn the completion credits. \u003c\/p\u003e\u003cp style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);box-sizing:border-box;color:rgb(65, 65, 65);font-family:sans-serif;font-size:14px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;margin:0px revert revert;orphans:2;padding:0px;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"\u003e\u003cstrong style=\"box-sizing:border-box;font-style:inherit;font-weight:revert;\"\u003eCourse Objectives\u003c\/strong\u003e\u003c\/p\u003e\u003cul style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);box-sizing:border-box;color:rgb(38, 38, 38);display:revert;font-family:Arial, Helvetica, sans-serif;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;list-style-image:revert;list-style-position:revert;list-style-type:disc;margin:revert;orphans:2;padding:0px 0px 0px revert;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"\u003e\n\u003cli\u003eDefine the key stages involved in the complete ASIC design flow.\u003c\/li\u003e\n\u003cli\u003eExplain the transitions from specification to architecture and RTL design.\u003c\/li\u003e\n\u003cli\u003eDescribe the role of functional verification and gate-level simulation in ensuring design correctness. \u003c\/li\u003e\n\u003cli\u003eUnderstand the importance of DFT and STA in achieving testability and timing closure.\u003c\/li\u003e\n\u003cli\u003eIdentify the major steps in physical design including design, including layout and GDS-II generation. \u003c\/li\u003e\n\u003c\/ul\u003e\u003cp style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);box-sizing:border-box;color:rgb(38, 38, 38);font-family:Arial, Helvetica, sans-serif;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;margin:revert;orphans:2;padding:0px;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"\u003e \u003c\/p\u003e\u003cp style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);box-sizing:border-box;color:rgb(65, 65, 65);font-family:sans-serif;font-size:14px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;margin:0px revert revert;orphans:2;padding:0px;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"\u003e\u003cstrong style=\"box-sizing:border-box;font-style:inherit;font-weight:revert;\"\u003eCourse Duration\u003c\/strong\u003e\u003c\/p\u003e\u003cp style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);box-sizing:border-box;color:rgb(65, 65, 65);font-family:sans-serif;font-size:14px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;margin:0px revert revert;orphans:2;padding:0px;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"\u003e\u003cstrong style=\"box-sizing:border-box;font-style:inherit;font-weight:revert;\"\u003e60 Minutes\u003c\/strong\u003e\u003c\/p\u003e\u003cp style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);box-sizing:border-box;color:rgb(65, 65, 65);font-family:sans-serif;font-size:14px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;margin:0px revert revert;orphans:2;padding:0px;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"\u003e \u003c\/p\u003e\u003cp style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);box-sizing:border-box;color:rgb(65, 65, 65);font-family:sans-serif;font-size:14px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;margin:0px revert revert;orphans:2;padding:0px;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"\u003e\u003cstrong style=\"box-sizing:border-box;font-style:inherit;font-weight:revert;\"\u003eTarget Audience\u003c\/strong\u003e\u003c\/p\u003e\u003cp style=\"-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);box-sizing:border-box;color:rgb(65, 65, 65);font-family:sans-serif;font-size:14px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;margin:0px revert revert;orphans:2;padding:0px;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"\u003e\u003cspan style=\"background-color:rgb(255,255,255);color:rgb(65,65,65);font-size:14px;\"\u003e\u003cspan style=\"-webkit-text-stroke-width:0px;display:inline !important;float:none;font-family:sans-serif;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:left;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;\"\u003eEntry level engineers, technicians, students or any individuals working directly in the semiconductor industry\u003c\/span\u003e\u003c\/span\u003e\u003c\/p\u003e","brand":"Maven Silicon","offers":[{"title":"Default Title","offer_id":67783419691186,"sku":"21585","price":0.0,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0121\/9441\/4651\/files\/800x800_SEMIU_Shopify_800x800_SEMIU_Shopify_VLSI-2_fad9a148-c899-4415-bf9a-88ae9df6658c.jpg?v=1792710307","url":"https:\/\/store-us.semi.org\/products\/vlsi-asic-design-flow-overview","provider":"semi.org","version":"1.0","type":"link"}