SEMI 3D5 - Guide for Metrology Techniques to be Used in Measurement of Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures -

Abstract

This Guide will assist the user in selection and use of tools for performing measurements of geometrical parameters of an individual through-silicon via (TSV), or of an array of TSVs. TSVs are expected to be a critical element in future three-dimensional stacked integrated circuit (3DS-IC) packaging. Advanced TSV designs with higher aspect ratios and smaller diameters may challenge TSV metrology techniques. This Guide will address the various metrology techniques that are currently available that enable TSV dimensional measurements. This Guide can also assist producers and users of TSV metrology to develop products and conduct meaningful evaluations.

This Guide focuses on the geometrical parameters of the openings (i.e., holes) in thin silicon slices, within which the conductive vias will be constructed. Additional layers on the surface of the silicon wafer, such as a hard mask, may be present; such layers may affect the performance of the metrology tools described below.

Referenced SEMI Standards (purchase separately)
SEMI 3D1 — Terminology for Through Silicon via Metrology
SEMI M59 — Terminology for Silicon Technology

Revision History
SEMI 3D5-0224 (technical revision)
SEMI 3D5-0314 (Reapproved 1218)
SEMI 3D5-0314 (technical revision)
SEMI 3D5-0613 (first published)

Interested in purchasing additional SEMI Standards? Consider SEMIViews, an online portal with access to over 1000 Standards.

Refund Policy: Due to the nature of our products, SEMI has a no refund/no exchange policy. Please make sure that you have reviewed your order prior to finalizing your purchase. All sales are final.