3D00400 - SEMI 3D4 - Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks

Volume(s): 3D-IC
Language: English
Type: Single Standards Download (.pdf)

Control of parameters such as bonded wafer stack (BWS) thickness, total thickness variation (TTV), bow, warp/sori, and flatness, is essential to successful implementation of a wafer bonding process. These parameters provide meaningful information about the quality of the wafer thinning process (if used), the uniformity of the bonding process, and the amount of deformation induced to the wafer stack by the bonding process. Total thickness variation is also critical in certain bonded wafer manufacturing process steps, since non-planarity can lead to problems in subsequent processing steps, including lithographic overlay and intermittent electrical contact between metal layers in the bonded wafers. This Guide provides a description of tools that can be used to determine these key parameters before, during, and after the process steps involved in wafer bonding.


This Guide provides examples of the capabilities and limitations of various measurement technologies applicable to BWS as well as their suitability for different applications.


The Guide describes metrology techniques that are applicable to both temporary and permanently bonded wafer stacks.


This Guide is complementary to existing SEMI Test Methods for measuring these parameters on single wafers, in some cases extending existing metrology techniques to a bonded wafer stack and in other cases describing metrology techniques specific to a bonded wafer stack.


The Guide focuses on general measurement techniques including IR laser profiling, white light confocal microscopy, visible and IR interferometry, capacitance, back-pressure, and acoustic metrology. Each technology has unique strengths and weaknesses—some rely on front-surface illumination, others on back-surface illumination. Some techniques can measure the thicknesses of individual layers in the bonded wafer stack, and some are additionally capable of measuring surface nanotopography.


The metrology examples provided in this Guide originated from industry experts and are believed to be representative of tool performance as of the year 2012. However, as tool and measurement techniques continue to evolve and improve, BWS measurement performance may surpass what is contained in this Guide. The user should investigate metrology suppliers’ current capabilities.


The measurements described in this Guide are known to be applicable to bonded wafer stacks with thickness in the range of 750 µm to 1550 µm.


A wafer stack, as considered in this Guide may include two wafers, where one is a device wafer, and one wafer is a carrier wafer. The wafer stack may include one bonding layer. Bonded wafers may be classified as either temporarily bonded (i.e., a device to a carrier wafer) or permanently bonded. Temporary bonding uses a temporary adhesive that can be reversed using a chemical, optical, and/or mechanical process; permanent bonding could be adhesive, oxide, or metal-metal (e.g., Cu-Cu). Two representative two-wafer stacks are depicted in Figures 1 and 2. The first stack (see Figure 1) is a bonded pair of 775 µm thick wafers following TSV formation and the bonding operation. The second stack (see Figure 2) is a bonded wafer stack with a top wafer thinned to ~50 µm, and bonded on top of a 775 µm wafer using a temporary adhesive.


Referenced SEMI Standards

SEMI 3D2 — Specification for Glass Carrier Wafers for 3DS-IC Applications
SEMI 3D8 — Guide for Describing Silicon Wafers for use as 300 mm Carrier Wafers in a 3DS-IC Temporary Bond-Debond (TBDB) Process
SEMI 3D12 — Guide for Measuring Flatness and Shape of Low Stiffness Wafers
SEMI HB1 — Specifications for Sapphire Wafers Intended for Use for Manufacturing High Brightness-Light Emitting Diode Devices
SEMI M49 — Guide for Specifying Geometry Measurement Systems for Silicon Wafers for the 130 nm to 16 nm Technology Generations
SEMI M59 — Terminology for Silicon Technology
SEMI M71 — Specification for Silicon-on-Insulator (SOI) Wafers for CMOS LSI
SEMI M78 — Guide for Reporting Wafer Nanotopography of Unpatterned Silicon Wafers for the 130 nm to 22 nm Generations in High Volume Manufacturing
SEMI MF533 — Test Method for Thickness and Thickness Variation of Silicon Wafers
SEMI MF1390 — Test Method for Measuring Bow and Warp on Silicon Wafers by Automated Noncontact Scanning
SEMI MF1451 — Test Method for Measuring Sori on Silicon Wafers by Automated Noncontact Scanning

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