SEMI 3D9 - Guide for Describing Materials Properties for a 300 mm 3DS-IC Wafer Stack -

Abstract

NOTICE: This Document was reapproved with minor editorial changes.

This Guide is intended to address the needs of the 3D Stacked IC (3DS-IC) industry by providing the tools needed to procure wafer stacks to be used in a 3DS-IC process.

Scope

This Guide provides the tools to describe wafer stacks in a 3DS-IC process. A wafer stacking process takes two or more intermediate wafers and forms a stack, which can then be further processed as if it were a single wafer. After bonding the dimensions of the stack will no longer conform to standard thickness and/or diameter.

This Guide describes wafer stacks with nominal diameter of 300 mm, although the actual stack diameter may differ due to process and functional variation.

The diameters of the different wafers that comprise the stack may differ from each other.

Referenced SEMI Standards

SEMI 3D4 — Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks

SEMI M1 — Specification for Polished Single Crystal Silicon Wafers

SEMI M45 — Specification for 300 mm Wafer Shipping System

SEMI M59 — Terminology for Silicon Technology

SEMI MF534 — Test Method for Bow of Silicon Wafers

SEMI MF657 — Test Method for Measuring Warp and Total Thickness Variation on Silicon Wafers by Noncontact Scanning

SEMI MF1390 — Test Method for Measuring Bow and Warp on Silicon Wafers by Automated Noncontact Scanning

SEMI MF1451 — Test Method for Measuring Sori on Silicon Wafers by Automated Noncontact Scanning

SEMI T7 — Specification for Back Surface Marking of Double-Side Polished Wafers with a Two-Dimensional Matrix Code Symbol

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