SEMI 3D13 - Guide for Measuring Voids in Bonded Wafer Stacks -

Member Price: $138.00
Non-Member Price: $180.00

Volume(s): 3D-IC
Language: English
Type: Single Standards Download (.pdf)
SEMI Standards Copyright Policy/License Agreements

Title: SEMI 3D13-0715 (Reapproved 0222) - Current



This Guide will assist users in selection and use of bond-void metrology equipment and a protocol for performing bond-void measurements based on their application. New bonding processes and applications are sensitive to significantly smaller voids than bonding processes currently used for 3DS-IC package sealing.

This Guide is based on experimental data on 300-mm diameter silicon wafer pairs. The inspection and metrology tools covered include only commercial instruments available in the 2012–2014 time frame. The wafer bonding technique used was oxide bonding. The experimental data were provided by volunteer participants in this study and have not been independently verified.

This Guide covers the purpose and results of the experimental study. Detailed explanation of the principles of operation and construction of the instruments used is beyond the scope of this Guide.


The potential and actual effects of bond voids on the performance and reliability of fabricated devices are beyond the scope of this Guide.


The scope of this study does not extend to recommendations as to which techniques may be less or more appropriate for particular manufacturing processes, and no such recommendations are provided herein.


Referenced SEMI Standards (purchase separately)

SEMI 3D4 — Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Warp/Sori, and Flatness of Bonded Wafer Stacks

SEMI M1 — Specification for Polished Single Crystal Silicon Wafers


Revision History

SEMI 3D13-0715 (Reapproved 0222)

SEMI 3D13-0715 (first published)

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