SEMI 3D18 - Guide for Wafer Edge Trimming for 3DS-IC Process -

Member Price: $138.00
Non-Member Price: $180.00

Volume(s): 3D-IC
Language: English
Type: Single Standards Download (.pdf)
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Title: SEMI 3D18-1018 - Current



3DS-IC wafer edge trimming process is a key step for successful wafer thinning after the wafer bonded in the 3DS-IC process.

This Guide provides a feasible approach to perform the wafer edge trimming.

This Document provides guidance for specifying edge trimming and resultant particle count to ensure the successful wafer thinning process after the wafer edge trimming.

This Document covers guidance for specifying wafer edge trimming and resultant particle count to provide a feasible approach in edge trimming process.

The trimming width, depth, and resultant particle size and count are addressed in this Guide. The outcome of this applicable wafer edge trimming approach will be helpful to the subsequent wafer thinning process in the 3DS-IC process.

Referenced SEMI Standards

SEMI 3D6 — Guide for CMP and Micro-Bump Processes for Frontside Through Silicon Via (TSV) Integration

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