SEMI 3D20 - Specification for Panel Characteristics for Panel Level Packaging (PLP) Applications -

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Non-Member Price: $180.00

Volume(s): 3D-IC
Language: English
Type: Single Standards Download (.pdf)
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Revision: SEMI 3D20-0921 - Current



Panel level packaging (PLP) is projected to become a critical packaging process. This Specification identifies the physical properties that must be specified for the semiconductor industry to produce an equipment set for successful implementation of PLP. Many of the applications for panel packaging lines include fan-out technology applications.

To permit common processing equipment, standardized panel (largest external) dimensions (whether with or without process carrier) are essential. As this technology has developed, numerous panel sizes, thickness, warpage, and mass are being investigated delaying the introduction of the technology and requiring customization of equipment and processes for each panel type.

This Specification focuses on panel (largest external) dimensions (with or without process carrier), panel thickness, warpage, and mass, for use in PLP applications.

The term panel is used to include panel (largest external) dimensions (with or without process carrier). Other parameters are included as an Appendix to this Specification.

Referenced SEMI Standards (purchase separately)

SEMI 3D12 — Guide for Measuring Flatness and Shape of Low Stiffness Wafers

SEMI G83 — Specification for Bar Code Marking of Product Packages

SEMI M1 — Specification for Polished Single Crystal Silicon Wafers

SEMI M12 — Specification for Serial Alphanumeric Marking of the Front Surface of Wafers

SEMI T7 — Specification for Back Surface Marking of Double-Side Polished Wafers with a Two-Dimensional Matrix Code Symbol

Revision History

SEMI 3D20-0921 (technical revision)

SEMI 3D20-0719 (first published)

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