Advanced Packaging & Material Characterization for Microelectronics EU/Asia 2/24/25

Advanced Packaging & Material Characterization for Microelectronics Asia & EU

Dates & Times

Feb 24th & Feb 25th, 2025

2:00 PM– 6:00 PM PST 

2:00 PM– 6:00 PM PST

Location

Webinar 

Pricing

Members: $599

Non-Members: $649

Strengthen your knowledge & skills by learning about new packaging technologies in Fan-in, Fan-out WLP, Embedded packaging technology System on Chip, System in Package, 3d IC, WLP, TSV, and more. Packaging knowledge is a must for professionals in the semiconductor industry. The first part of the course dives into advanced packaging and the second part focuses on the design of electrical and thermal processes which are used to enhance the electrical, thermal, and reliability performance of the package.

The principles of microelectronics packaging range from electronics, mechanical, and material to chemical engineering. Due to this multi-discipline nature, many industry professionals don’t know what they don’t know as they do not undergo multi-discipline training to understand these principles. This course provides the necessary technical knowledge for industry professionals.

Learning Objectives:

• Understand the principles in the evolution of IC packaging and how the semiconductor industry has evolved with time.
• Understand the principles of Interconnections ranging from TAB, and Wirebond to various Flip Chip bonding, such as thermocompression bonding with NCP, C4, ACF for manufacturing and R&D development.
• Review the interposer of leadframe, ceramic, and flex to BT substrates for Microelectronics packaging.
• Explain the assembly flow and new assembly techniques from back grinding to singulation.
• Describe the material characterization from bulk to interfaces to reduce stress and enhance interfacial adhesion for reliability enhancement.

Course Topics:

• Advanced packaging and material characterization.
• Packaging principles and how packaging evolves into heterogeneous packaging.
• Packaging concepts such as Fan-in, Fan-out, WLP, Embedded packaging technology, 3d packaging, TSV.
• Wirebond and Flip chip interconnect technologies inclusive of interposer technologies, such as leadframe, ceramic, flex and substrate.
• Assembly processes from back grinding to singulation for QFP and FBGA packages.
• Material characterization to select materials to reduce stress and strengthen the interface for reliability enhancement.

Who should Attend:

This course is intended for both manufacturing and R&D know-how in IC packaging professionals, including but not limited to:

• Directors
• Managers
• Process Engineers
• R&D Engineers
• Sales and Application Engineers who supply packaging materials and tools

Cancellation and Rescheduling Policies   

• Registrants may cancel or reschedule a class no less than 30 days before the class start date.
• Cancellations received after the stated deadline will not be eligible for a refund.
• Cancellations will be accepted via email to semiu-support@semi.org
• All refund requests will be credited to the original payment method used for payment.
• SEMI reserves the right to cancel any course due to low enrollment or other circumstances that would make the event unavailable 7 business days before the class’s start date.
• If SEMI cancels a class, the registrants will be offered a full refund.