SEMI M1 - Specification for Polished Single Crystal Silicon Wafers -

Member Price: $252.00
Non-Member Price: $335.00

Volume(s): Materials
Language: English
Type: Single Standards Download (.pdf)
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Revision: SEMI M1-0918 - Current



Single crystal silicon wafers are utilized for essentially all integrated circuits and many other semiconductor devices. To permit common processing equipment to be used in multiple device fabrication lines, it is essential for the wafer dimensions to be standardized.

In addition, as technology advances to smaller and smaller dimensions for the elements of high-density integrated circuits, it has become of interest to standardize additional properties of the wafers.

This Specification provides the essential dimensional and certain other common characteristics of silicon wafers, including polished wafers as well as substrates for epitaxial and certain other kinds of silicon wafers.

This Specification covers ordering information and certain requirements for high-purity (electronic grade), single crystal polished silicon wafers used in semiconductor device and integrated circuit manufacturing. Such wafers are usually sliced from cylindrical single-crystal ingots that have been ground to a uniform diameter prior to slicing. This Specification also covers ordering information and certain requirements for electronic grade silicon wafers intended for use as substrates (or starting wafers) for other kinds of wafers, including epitaxial, annealed, and SOI wafers.

Standardized dimensional requirements are provided for a large number of categories of standardized polished wafers as listed in the tables in § 6.

Values given for thickness, total thickness variation (TTV), bow, and warp apply only to wafers prior to application of back surface films, extrinsic gettering treatments, or other thermal treatments.

This Specification applies specifically to prime silicon wafers with at least one chem-mechanically polished surface. Ground, lapped, and unpolished wafers are not covered but this Specification may provide guidance in connection with their procurement.

This Specification also provides guides for the specification of 300 and 450 mm diameter prime silicon wafers for the 32, 22, and 16 nm technology generations. These are included in Related Information 1.

This Specification does not cover requirements for the following related types of silicon materials and wafers:

  • Polycrystalline silicon (see SEMI M16 or JEITA EM-3601A),

  • Epitaxial wafers (see SEMI M62),

  • Epitaxial wafers with buried layer (see SEMI M61),

  • Test wafers (see SEMI M8),

  • Premium wafers (see SEMI M24),

  • Reclaimed wafers (see SEMI M38),

  • Annealed wafers (see SEMI M57),

  • SOI wafers (see SEMI M41, SEMI M71, or JEITA EM-3603B), and

  • Solar-grade silicon wafers (see SEMI PV22).

They do, however, provide the ordering information for test, premium, and reclaimed wafers, as well as the ordering information for the polished substrates and starting wafers used to prepare epitaxial, annealed, and SOI wafers.

For reference purposes, U.S. customary units shall be used for wafers of 2 inch and 3 inch nominal diameters, and SI (system international, commonly called metric) units for 100 mm and larger diameter wafers.

Referenced SEMI Standards
(purchase separately)

SEMI M8 — Specification for Polished Monocrystalline Silicon Test Wafers
SEMI M12 — Specification for Serial Alphanumeric Marking of the Front Surface of Wafers
SEMI M13 — Specification for Alphanumeric Marking of Silicon Wafers
SEMI M16 — Specification for Polycrystalline Silicon
SEMI M18 — Guide for Developing Specification Forms for Order Entry of Silicon Wafers
SEMI M20 — Practice for Establishing a Wafer Coordinate System
SEMI M24 — Specification for Polished Monocrystalline Silicon Premium Wafers
SEMI M26 — Guide for the Re-Use of 100, 125, 150, and 200 mm Wafer Shipping Boxes Used to Transport Wafers
SEMI M35 — Guide for Developing Specifications for Silicon Wafer Surface Features Detected by Automated Inspection
SEMI M38 — Specification for Polished Reclaimed Silicon Wafers
SEMI M40 — Guide for Measurement of Roughness of Planar Surfaces on Silicon Wafers
SEMI M41 — Specification of Silicon-On-Insulator (SOI) for Power Device/ICs
SEMI M43 — Guide for Reporting Wafer Nanotopography
SEMI M44 — Guide to Conversion Factors for Interstitial Oxygen in Silicon
SEMI M45 — Specification for 300 mm Wafer Shipping System
SEMI M49 — Guide for Specifying Geometry Measurement Systems for Silicon Wafers for the 130 nm to 16 nm Technology Generations
SEMI M53 — Practice for Calibrating Scanning Surface Inspection Systems Using Certified Depositions of Monodisperse Reference Spheres on Unpatterned Semiconductor Wafer Surfaces
SEMI M57 — Guide for Specifying Silicon Annealed Wafers
SEMI M58 — Test Method for Evaluating DMA-Based Particle Deposition Systems and Processes
SEMI M59 — Terminology for Silicon Technology
SEMI M61 — Specification for Silicon Epitaxial Wafers with Buried Layers
SEMI M62 — Specification for Silicon Epitaxial Wafers
SEMI M67 — Practice for Determining Wafer Near-Edge Geometry from a Measured Thickness Data Array Using the ESFQR, ESFQD and ESBIR Metrics
SEMI M68 — Test Method for Determining Wafer Near-Edge Geometry from a Measured Height Data Array Using a Curvature Metric, ZDD
SEMI M70 — Test Method for Determining Wafer-Near-Edge Geometry Using Partial Wafer Site Flatness
SEMI M71 — Specification for Silicon-On-Insulator (SOI) Wafers for CMOS LSI
SEMI M73 — Test Methods for Extracting Relevant Characteristics from Measured Wafer Edge Profiles
SEMI M77 — Test Method for Determining Wafer Near-Edge Geometry Using Roll-Off Amount, ROA
SEMI M78 — Guide for Determining Nanotopography of Unpatterned Silicon Wafers for the 130 nm to 22 nm Generations in High Volume Manufacturing
SEMI M85 — Guide for the Measurement of Trace Metal Contamination on Silicon Wafers Surface by Inductively Coupled Plasma Mass Spectrometry
SEMI MF26 — Test Method for Determining the Orientation of a Semiconductive Single Crystal
SEMI MF28 — Test Method for Minority-Carrier Lifetime in Bulk Germanium and Silicon by Measurement of Photoconductive Decay
SEMI MF42 — Test Method for Conductivity Type of Extrinsic Semiconducting Materials
SEMI MF81 — Test Method for Measuring Radial Resistivity Variation on Silicon Wafers
SEMI MF84 — Test Method for Measuring Resistivity of Silicon Wafers with an In-Line Four-Point Probe
SEMI MF391 — Test Method for Minority Carrier Diffusion Length in Extrinsic Semiconductors by Measurement of Steady-State Surface Photovoltage
SEMI MF523 — Practice for Unaided Visual Inspection of Polished Silicon Wafer Surfaces
SEMI MF525 — Test Method for Measuring Resistivity of Silicon Wafers Using a Spreading Resistance Probe
SEMI MF533 — Test Method for Thickness and Thickness of Variation of Silicon Wafers
SEMI MF671 — Test Method for Measuring Flat Length on Wafers of Silicon and Other Electronic Materials
SEMI MF673 — Test Method for Measuring Resistivity of Semiconductor Slices or Sheet Resistance of Semiconductor Films with a Noncontact Eddy-Current Gage
SEMI MF847 — Test Method for Measuring Crystallographic Orientation of Flats on Single Crystal Silicon Wafers by X-Ray Techniques
SEMI MF928 — Test Method for Edge Contour of Circular Semiconductor Wafers and Rigid Disk Substrates
SEMI MF951 — Test Method for Determination of Radial Interstitial Oxygen Variation in Silicon Wafers
SEMI MF978 — Test Method for Characterizing Semiconductor Deep Levels by Transient Capacitance Techniques
SEMI MF1048 — Test Method for Measuring Reflective Total Integrated Scatter
SEMI MF1049 — Practice for Shallow Etch Pit Detection on Silicon Wafers
SEMI MF1152 — Test Method for Dimensions of Notches on Silicon Wafers
SEMI MF1188 — Test Method for Interstitial Oxygen Content of Silicon by Infrared Absorption with Short Baseline
SEMI MF1239 — Test Method for Oxygen Precipitation Characteristics of Silicon Wafers by Measurement of Interstitial Oxygen Reduction
SEMI MF1366 — Test Method for Measuring Oxygen Concentration in Heavily Doped Silicon Substrates by Secondary Ion Mass Spectrometry
SEMI MF1388 — Test Method for Generation Lifetime and Generation Velocity of Silicon Material by Capacitance-Time Measurements of Metal-Oxide-Silicon (MOS) Capacitors
SEMI MF1390 — Test Method for Measuring Bow and Warp on Silicon Wafers by Automated Noncontact Scanning
SEMI MF1391 — Test Method for Substitutional Atomic Carbon Content of Silicon by Infrared Absorption
SEMI MF1451 — Test Method for Measuring Sori on Silicon Wafers by Automated Noncontact Scanning
SEMI MF1528 — Test Method for Measuring Boron Contamination in Heavily Doped n-Type Silicon Substrates by Secondary Ion Mass Spectrometry
SEMI MF1530 — Test Method for Measuring Flatness, Thickness, and Total Thickness Variation on Silicon Wafers by Automated Noncontact Scanning
SEMI MF1535 — Test Method for Carrier Recombination Lifetime in Silicon Wafers by Noncontact Measurement of Photoconductivity Decay by Microwave Reflectance
SEMI MF1617 — Test Method for Measuring Surface Sodium, Aluminum, Potassium, and Iron on Silicon and Epi Substrates by Secondary Ion Mass Spectrometry
SEMI MF1619 — Test Method for Measurement of Interstitial Oxygen Content of Silicon Wafers by Infrared Absorption Spectroscopy with p-Polarized Radiation Incident at the Brewster Angle
SEMI MF1726 — Practice for Analysis of Crystallographic Perfection of Silicon Wafers
SEMI MF1727 — Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers
SEMI MF1809 — Guide for Selection and Use for Etching Solutions to Delineate Structural Defects in Silicon
SEMI MF1982 — Test Method for Analyzing Organic Contaminants on Silicon Wafer Surfaces by Thermal Desorption Gas Chromatography
SEMI MF2074 — Guide for Measuring Diameter of Silicon and Other Semiconductor Wafers
SEMI PV13 — Test Method for Contactless Excess-Charge-Carrier Recombination Lifetime Measurement in Silicon Wafers, Ingots, and Bricks Using an Eddy-Current Sensor
SEMI PV22 — Specification for Silicon Wafers for Use in Photovoltaic Solar Cells
SEMI T3 — Specification for Wafer Box Labels
SEMI T7 — Specification for Back Surface Marking of Double-sided Polished Wafers with a Two-Dimensional Matrix Code Symbol

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