SEMI M17 - Guide for a Universal Wafer Grid -

Abstract

Maximum allowable slip and other non-uniformly distributed defects are frequently specified when procuring polished and epitaxial silicon wafers. SEMI M62 specifies a maximum allowable fraction of the epitaxial wafer surface area that can contain slip.

 

This Guide provides a design for and guidance for use of a wafer grid that facilitates the determination of the fraction of the wafer surface area covered by observed defects.

This Guide defines a grid pattern that is useful for quantifying surface defects on a nominally circular semiconductor wafer. The grid is defined such that it contains 1000 elements of approximately equal area. Each grid element thus contains 0.1% of the total quality area of the surface being inspected. Defects that are non-uniformly distributed (e.g., slip) can be quantified in terms of the percent defective (or percent useful) area on the wafer surface.

 

The grid described is referenced to the center of the wafer. A concept of a ‘fixed quality area’ is used, based on nominal wafer diameter, such as is specified in SEMI M1.

 

Referenced SEMI Standards (purchase separately)

SEMI M1 — Specification for Polished Single Crystal Silicon Wafers

SEMI M59 — Terminology for Silicon Technology

SEMI M62 — Specification for Silicon Epitaxial Wafers

SEMI MF154 — Guide for Identification of Structures and Contaminants Seen on Specular Silicon Surfaces

SEMI MF1725 — Practice for Analysis of Crystallographic Perfection of Silicon Ingots

SEMI MF1726 — Practice for Analysis of Crystallographic Perfection of Silicon Wafers

SEMI MF1809 — Guide for Selection and Use of Etching Solutions to Delineate Structural Defects in Silicon

 

Revision History

SEMI M17-1110 (Reapproved 1121)

SEMI M17-1110 (Reapproved 1015)

SEMI M17-1110 (technical revision)

SEMI M17-0704 (technical revision)

SEMI M17-0998 (technical revision)

SEMI M17-90 (first published)

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