SEMI M49 - Guide for Specifying Geometry Measurement Systems for Silicon Wafers for the 130 nm to 16 nm Technology Generations

Volume(s): Materials
Language: English
Type: Single Standards Download (.pdf)
Abstract

This Standard was technically approved by the Silicon Wafer Global Technical Committee. This edition was approved for publication by the global Audits and Reviews Subcommittee on August 17, 2018. Available at www.semiviews.org and www.semi.org in September 2018; originally published November 2001; previously published October 2016.

This Guide provides recommendations for specifying measurement systems for geometry and flatness of silicon wafers of the 130, 90, 65, 45, 32, 22, and 16 nm technology generation as anticipated by the International Technology Roadmap for Semiconductors (ITRS) and in the forecasts of the major manufacturers of semiconductor devices. Wafer parameters as defined by SEMI M1, SEMI M8, SEMI M11, SEMI M24, or SEMI M38 are specified by customers of silicon wafer suppliers and are usually part of Certificates of Compliance. Suppliers of silicon wafers and their customers might measure these parameters using equipment provided by different manufacturers of such equipment or using different generations of equipment of one supplier. Agreement on basic features and capability of such measurement systems improves data exchange and interpretation of data as well as procurement of appropriate measurement systems.

This Guide outlines and recommends basic specifications for systems for measuring geometry and flatness of silicon wafers of the 130, 90, 65, 45, 32, 22, and 16 nm technology generation.

This Guide applies to measurement systems used for verifying the quality parameters geometry and flatness in large scale production of bare polished or epitaxial silicon wafers the backside of which may be acid etched and/or covered by unpatterned, homogeneous layers of, for example, poly-Si or low temperature oxide (LTO). Artifacts (e.g., reference materials) for calibrating a measurement system might have different properties.

This Guide also applies to measurement systems that provide only a subset of the measurement features outlined in this Guide.

The Guide does not apply to measurement systems used to control intermediate process steps during Si wafer manufacturing. However, it may be completely or partly used for measurement systems for those applications provided corresponding constraints are appropriately identified.

The Guide also does not apply to measurement systems for SOI wafers or patterned wafers.

Referenced SEMI Standards

SEMI E1.9 — Mechanical Specification for Cassettes Used to Transport and Store 300 mm Wafers
SEMI E5 — Specification for SEMI Equipment Communications Standard 2 Message Content (SECS-II)
SEMI E10 — Specification for Definition and Measurement of Equipment Reliability, Availability, and Maintainability (RAM) and Utilization
SEMI E19 — Specification for Standard Mechanical Interface (SMIF)
SEMI E30 — Specification for the Generic Model for Communications and Control of Manufacturing Equipment (GEM)
SEMI E37 — High Speed SECS Message Services (HSMS) Generic Services
SEMI E47 — Specification for 150 mm/200 mm Pod Handles
SEMI E47.1 — Mechanical Specification for FOUPS Used to Transport and Store 300 mm Wafers
SEMI E58 — Automated Reliability, Availability, and Maintainability Standard (ARAMS): Concepts, Behavior, and Services
SEMI E89 — Guide for Measurement System Analysis (MSA)
SEMI E158 — Mechanical Specification for Fab Wafer Carrier Used to Transport and Store 450 mm Wafers (450 FOUP) and Kinematic Coupling
SEMI E159 — Mechanical Specification for Multi Application Carrier (MAC) Used to Transport and Ship 450 mm Wafers
SEMI M1 — Specification for Polished Single Crystal Silicon Wafers
SEMI M8 — Specification for Polished Monocrystalline Silicon Test Wafers
SEMI M12 — Specification for Serial Alphanumeric Marking of the Front Surface of Wafers
SEMI M13 — Specification for Alphanumeric Marking of Silicon Wafers
SEMI M24 — Specification for Polished Monocrystalline Silicon Premium Wafers
SEMI M31 — Specification for Mechanical Features of Front-Opening Shipping Box Used to Transport and Ship 300 mm Wafers
SEMI M38 — Specification for Polished Reclaimed Silicon Wafers
SEMI M43 — Guide for Reporting Wafer Nanotopography
SEMI M59 — Terminology for Silicon Technology
SEMI M62 — Specification for Silicon Epitaxial Wafers
SEMI M67 — Practice for Determining Wafer Near-Edge Geometry from a Measured Thickness Data Array Using the ESFQR, ESFQD and ESBIR Metrics
SEMI M68 — Practice for Determining Wafer Near-Edge Geometry from a Measured Height Data Array Using a Curvature Metric, ZDD
SEMI M73 — Test Methods for Extracting Relevant Characteristics from Measured Wafer Edge Profiles
SEMI M80 — Specification for Front-Opening Shipping Box Used to Transport and Ship 450 mm Wafers
SEMI MF42 — Test Method for Conductivity Type of Extrinsic Semiconducting Materials
SEMI MF84 — Test Method for Measuring Resistivity of Silicon Wafers with an In-Line Four-Point Probe
SEMI MF534 — Test Method for Bow of Silicon Wafers
SEMI MF657 — Test Method for Measuring Warp and Total Thickness Variation on Silicon Wafers by Noncontact Scanning
SEMI MF671 — Test Method for Measuring Flat Length on Wafers of Silicon and Other Electronic Materials
SEMI MF673 — Test Method for Measuring Resistivity of Semiconductor Wafers or Sheet Resistance of Semiconductor Films with a Noncontact Eddy-Current Gauge
SEMI MF928 — Test Method for Edge Contour of Circular Semiconductor Wafers and Rigid Disk Substrates
SEMI MF1152 — Test Method for Dimensions of Notches on Silicon Wafers
SEMI MF1390 — Test Method for Measuring Bow and Warp on Silicon Wafers by Automated Noncontact Scanning
SEMI MF1451 — Test Method for Measuring Sori on Silicon Wafers by Automated Noncontact Scanning
SEMI MF1530 — Test Method for Measuring Flatness, Thickness, and Thickness Variation on Silicon Wafers by Automated Noncontact Scanning
SEMI MF2074 — Guide for Measuring Diameter of Silicon and Other Semiconductor Wafers
SEMI T7 — Specification for Back Surface Marking of Double-Side Polished Wafers with a Two-Dimensional Matrix Code Symbol

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