M05200 - SEMI M52 - Guide for Specifying Scanning Surface Inspection Systems for Silicon Wafers for the 130 nm to 5 nm Technology Generations
This Guide provides recommendations for specifying scanning surface inspection systems (SSIS) for the 130, 90, 65, 45, 32, 22, 16, 11, 7, and 5 nm technology generations. The number and size of localized light scatterers (LLS) on silicon wafers are specified by customers of silicon wafer suppliers and are usually part of Certificates of Compliance. Suppliers of silicon wafers and their customers might measure these parameters using measurement systems provided by different manufacturers of such systems or using different generations of measurement systems from one supplier. Therefore, standardization of various aspects of such measurement systems both improves data exchange and data interpretation and aids in procurement of appropriate measurement systems.
This Guide outlines and recommends basic specifications for SSIS equipment used for the 130, 90, 65, 45, 32, 22, 16, 11, 7, and 5 nm technology generations. Recommendations for the 130 to 11 nm generations are unchanged from previous versions of this Guide. The 7 and 5 nm node characteristics are taken from the 2018 edition of the International Roadmap for Devices and Systems (IRDS), the successor to the International Technology Roadmap for Semiconductors (ITRS).
The Guide covers generic equipment characteristics of (Table 1), materials to be measured by (Table 2), and metrology specific equipment characteristics of (Table 3) measurement systems used for verifying the quality parameter LLS counts per wafer in large scale production of bare polished or epitaxial surfaces of silicon wafers, the back surface of which may be polished or acid etched, either bare or covered by an unpatterned, homogeneous layer of polysilicon or low temperature oxide (LTO). Reference materials for calibrating measurement systems might have different properties.
The Guide also applies to measurement systems that provide only a subset of the measurement features outlined in Table 3.
This Guide does not apply to measurement systems used to control intermediate process steps during silicon wafer manufacturing. However, it may be completely or partly used for measurement systems for those applications provided corresponding constraints are appropriately identified.
This Guide does not apply to measurement systems for silicon on insulator (SOI) wafers or patterned wafers.
Referenced SEMI Standards (purchase separately)
SEMI E1.9 — Mechanical Specification for Cassettes Used to Transport and Store 300 mm Wafers
SEMI E5 — Specification for SEMI Equipment Communications Standard 2 Message Content (SECS-II)
SEMI E10 — Specification for Definition and Measurement of Equipment Reliability, Availability, and Maintainability (RAM) and Utilization
SEMI E19 — Specification for Standard Mechanical Interface (SMIF)
SEMI E30 — Specification for the Generic Model for Communications and Control of Manufacturing Equipment (GEM)
SEMI E37 — Specification for High Speed SECS Message Services (HSMS) Generic Services
SEMI E47 — Specification for 150 mm/200 mm Pod Handles
SEMI E47.1 — Mechanical Specification for FOUPs Used to Transport and Store 300 mm Wafers
SEMI E58 — Automated Reliability, Availability, and Maintainability Standard (ARAMS): Concepts, Behavior, and Services
SEMI E89 — Guide for Measurement System Analysis (MSA)
SEMI E158 — Specification for Mechanical Features of Fab Wafer Carrier Used to Transport and Store 450 mm Wafers (450 FOUP) and Kinematic Coupling
SEMI E159 — Specification for Mechanical Features of Multi Application Carrier (MAC) Used to Transport and Ship 450 mm Wafers
SEMI M1 — Specification for Polished Single Crystal Silicon Wafers
SEMI M31 — Specification for Mechanical Features of Front-Opening Shipping Box Used to Transport and Ship 300 mm Wafers
SEMI M33 — Test Method for the Determination of Residual Surface Contamination on Silicon Wafers by Means of Total Reflection X-Ray Fluorescence Spectroscopy (TXRF)
SEMI M35 — Guide for Developing Specifications for Silicon Wafer Surface Features Detected by Automated Inspection
SEMI M38 — Specification for Polished Reclaimed Silicon Wafers
SEMI M50 — Test Method for Determining Capture Rate and False Count Rate for Surface Scanning Inspection Systems by the Overlay Method
SEMI M53 — Practice for Calibrating Scanning Surface Inspection Systems Using Certified Depositions of Monodisperse Polystyrene Latex Sphere on Unpatterned Semiconductor Wafer Surfaces
SEMI M58 — Test Method for Evaluating DMA Based Particle Deposition Systems and Processes
SEMI M59 — Terminology for Silicon Technology
SEMI M80 — Specification for Front-Opening Shipping Box Used to Transport and Ship 450 mm Wafers
SEMI M52-0621 (technical revision)
SEMI M52-0214 (technical revision)
SEMI M52-0912 (technical revision)
SEMI M52-0412 (technical revision)
SEMI M52-0307 (technical revision)
SEMI M52-0706E (editorial revision)
SEMI M52-0706 (complete rewrite)
SEMI M52-0703 (technical revision)
SEMI M52-0303 (technical revision)
SEMI M52-1102 (first published)
|Interested in purchasing additional SEMI Standards? Consider SEMIViews, an online portal with access to over 1000 Standards.|
Refund Policy: Due to the nature of our products, SEMI has a no refund/no exchange policy. Please make sure that you have reviewed your order prior to finalizing your purchase. All sales are final.