SEMI M57 - Specification for Silicon Annealed Wafers

Volume(s): Materials
Language: English
Type: Single Standards Download (.pdf)
Abstract

This Standard was technically approved by the Silicon Wafer Global Technical Committee. This edition was approved for publication by the global Audits and Reviews Subcommittee on February 1, 2016. Available at www.semiviews.org and www.semi.org in March 2016; originally published July 2004; previously published April 2014.

 

A number of device manufacturers utilize silicon annealed wafers to gain improved device characteristics. This Specification provides information for developing specifications for silicon annealed wafers used to fabricate semiconductor devices and integrated circuits.

 

This Specification covers dimensional, electrical, chemical, and structural properties of silicon annealed wafers for 180 nm, 130 nm, 90 nm, (Table R1-1), 65 nm, 45 nm, 32 nm, (Table R1-2), and 22 nm (Table R1-3) device technology generations.

 

Based on the guidance herein, the user of this Document can generate specifications for silicon annealed wafers.

 

One of the reasons for using annealed wafers is to allow a reduction in the crystal originated pits (COP), also sometimes known as crystal originated particles, near the top surface region of the wafer. The width of the denuded zone (DZ) free of bulk micro defects (BMD) is also an important parameter.

 

Referenced SEMI Standards

SEMI M1 — Specification for Polished Single Crystal Silicon Wafers
SEMI M35 — Guide for Developing Specifications for Silicon Wafer Surface Features Detected by Automated Inspection
SEMI M45 — Specification for 300 mm Wafer Shipping System
SEMI M53 — Practice for Calibrating Scanning Surface Inspection Systems Using Certified Depositions of Monodisperse Reference Spheres on Unpatterned Semiconductor Wafer Surfaces
SEMI M58 — Test Method for Evaluating DMA Based Particle Deposition Systems and Processes
SEMI M59 — Terminology for Silicon Technology
SEMI MF81 — Test Method for Measuring Radial Resistivity Variation on Silicon Wafers
SEMI MF391 — Test Methods for Minority Carrier Diffusion Length in Extrinsic Semiconductors by Measurement of Steady-State Surface Photovoltage
SEMI MF523 — Practice for Unaided Visual Inspection of Polished Silicon Wafer Surfaces
SEMI MF951 — Test Method for Determination of Radial Interstitial Oxygen Variation in Silicon Wafers
SEMI MF1239 — Test Method for Oxygen Precipitation Characteristics of Silicon Wafers by Measurement of Interstitial Oxygen Reduction
SEMI MF1530 — Test Method for Measuring Flatness, Thickness, and Total Thickness Variation on Silicon Wafers by Automated Noncontact Scanning
SEMI MF1535 — Test Method for Carrier Recombination Lifetime in Electronic-Grade Silicon Wafers by Noncontact Measurement of Photoconductivity Decay by Microwave Reflectance
SEMI MF1617 — Test Method for Measuring Surface Sodium, Aluminum, Potassium, and Iron on Silicon and EPI Substrates by Secondary Ion Mass Spectroscopy
SEMI MF1726 — Practice for Analysis of Crystallographic Perfection of Silicon Wafers
SEMI MF1727 — Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers
SEMI MF1809 — Guide for Selection and Use for Etching Solutions to Delineate Structural Defects in Silicon
SEMI T3 — Specification for Wafer Box Labels
SEMI T7 — Specification for Back Surface Marking of Double-Side Polished Wafers with a Two-Dimensional Matrix Code Symbol

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