SEMI M66 - Test Method to Extract Effective Work Function in Oxide and High-K Gate Stacks Using the MIS Flat Band Voltage-Insulator Thickness Technique -

Abstract

Continued scaling of CMOS integrated circuit dimensions is reaching a point where materials changes as well as lithographic advances are required to meet the projections of Moore’s Law and the International Technology Roadmap for Semiconductors. As gate dielectric thickness approaches 1 nm, both the gate dielectric and electrode materials that have been in common usage—SiO2, and doped polysilicon—are displaying characteristics that are unacceptable for upcoming technology nodes. Research to find suitable replacements for the n+ and p+ polysilicon gate electrodes used in conventional CMOS is placing renewed emphasis on experimental determination of the effective gate electrode work function of candidate materials.

 

One aspect of the research for new gate electrode materials is that they may be required for use on either silicon dioxide (SiO2) gate dielectrics or on the high-κ gate dielectrics that are being developed to replace SiO2. While it might seem that gate electrode work function differences should depend only upon the properties of the gate electrode material and the silicon substrate, it has been shown that various metal-dielectric interactions may cause potential shifts that affect the effective work function. Thus consideration must be given to structures and analyses that properly take these effects into account.

Changes in process technology and wafer fabrication practice since these measurements were first widely used suggest a need for revised approaches to test structure fabrication and analysis. Definition of such changes is the purpose of this Test Method, which covers the measurement, analysis and reporting of effective gate electrode work function data by the flat band voltage-insulator thickness technique.

This Test Method covers determination of the effective work function of both oxide and high-κ gate stacks. While the basic technique is based upon the conventional MOS capacitor flat band voltage-dielectric thickness approach as outlined in SEMI MF1153, two features of the present test method are keys to its usefulness: (1) the ability to provide a demonstrably good estimate of effective work function from measurements on a single silicon wafer, and (2) the ability to separate and minimize the effects of interfacial and bulk charge distributions in a high-κ gate stack on the effective work function value. Both of these features depend upon the nature and fabrication of the test structures used for the test method. The nature of the samples is so important to the application of the method that the terraced oxide technique, an automated approach to fabrication of suitable test structures using standard tools available in modern wafer fabs, is outlined as part of the test method and alternative, but probably less accurate and less reproducible, approaches suitable for use in smaller facilities are outlined in Related Information 1.

 

Referenced SEMI Standards (purchase separately)

SEMI M59 — Terminology for Silicon Technology

SEMI MF1153 — Test Method for Characterization of Metal-Oxide-Silicon (MOS) Structures by Capacitance-Voltage Measurements

 

Revision History

SEMI M66-1110 (Reapproved 1121)

SEMI M66-1110 (Reapproved 1015)

SEMI M66-1110 (technical revision)

SEMI M66-0706E (editorial revision)

SEMI M66-0706 (first published)

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