SEMI M78 - Guide for Determining Nanotopography of Unpatterned Silicon Wafers for the 130 nm to 22 nm Generations in High Volume Manufacturing
This Standard was technically approved by the Silicon Wafer Global Technical Committee. This edition was approved for publication by the global Audits and Reviews Subcommittee on December 13, 2017. Available at www.semiviews.org and www.semi.org in June 2018; originally published November 2010.
Front-surface wafer height variations over specified distances need to be properly controlled to assure that wafers are acceptable for selected process steps. Nanotopography parameters are included in the International Technology Roadmap for Semiconductors (ITRS) since 2003. Nanotopography on a wafer surface prior to chemical-mechanical planarization (CMP) processes can result in variations of post-CMP film thickness with potential negative consequences for circuit performance, process cost and yield. Nanotopography features are characterized by their height variation within an area, and are discriminated from other features of similar height by their spatial wavelength range. Back-surface Nanotopography may also impact wafer suitability for selected process steps. This Guide may be applicable to either front- or back-surface measurements of Nanotopography.
This Guide provides procedures and a decision tree (see Figure 1) for selecting the different possible options in generating Nanotopography data. The key options used in the calculation are specified to define the data reported. This Guide is intended for use in the exchange of silicon wafers and is not intended for process development where a wider range of options and data reporting formats may be appropriate.
This Guide covers the determination and reporting of the Nanotopography of unpatterned silicon wafer surfaces for device generations from 130 nm to 22 nm. Typical examples include dips, bumps or waves on the wafer surface that have dominant spatial wavelengths less than 20 mm and vary in peak-to-valley (P-V) height from a few nanometers to several hundred nanometers.
This Guide specifies the technique for collecting and analyzing Nanotopography data.
Use of P-V metric is specified for Nanotopography quantification. An alternative deviation metric is described in Related Information 1.
Spatial representations of the defective areas on a wafer surface are outside the scope of this Guide.
Referenced SEMI Standards
SEMI M1 — Specification for Polished Single Crystal Silicon Wafers
SEMI M20 — Practice for Establishing a Wafer Coordinate System
SEMI M43 — Guide for Reporting Wafer Nanotopography
SEMI M49 — Guide for Specifying Geometry Measurement Systems for Silicon Wafers for the 130 nm to 16 nm Technology Generations
SEMI M59 — Terminology for Silicon Technology