MF097800 - SEMI MF978 - Test Method for Characterizing Semiconductor Deep Levels by Transient Capacitance Techniques

Volume(s): Silicon Materials & Process Control
Language: English
Type: Single Standards Download (.pdf)

This Standard was technically approved by the Silicon Wafer Global Technical Committee. This edition was approved for publication by the global Audits and Reviews Subcommittee on February 2, 2017. Available at and in March 2017; originally published by ASTM International as ASTM F978; previously published November 2011.


Deep-level defect measurement techniques such as isothermal transient capacitance (ITCAP) and DLTS utilize the ability of electrically active defects to trap free carriers and to re-emit them by thermal emission.


An analogous expression can be written for the whole emission rate. Analysis of the measured thermal emission rate in the depletion layer of a test device as a function of temperature leads to activation energies and effective capture cross sections of the defects present. The magnitude of the capacitance changes associated with the emission can be related to the densities of the defects present. The interest in measurement of deep levels in semiconductors stems from the following two related aspects:

Detection, identification, and control of unwanted native or process-induced impurities or defects; and Characterization and control of impurities specifically introduced for lifetime or other parameter control.


This Test Method covers three procedures for determining the density, activation energy, and prefactor of the exponential expression for the emission rate of deep-level defect centers in semiconductor depletion regions by transient-capacitance techniques.


Procedure A is the conventional, constant voltage, deep-level transient spectroscopy (DLTS) technique in which the temperature is slowly scanned and an exponential capacitance transient is assumed.


Procedure B is the conventional DLTS (Procedure A) with corrections for non-exponential transients due to heavy trap doping and incomplete charging of the depletion region.


Procedure C is a more precise referee technique that uses a series of isothermal transient measurements and corrects for the same sources of error as Procedure B.


Referenced SEMI Standards

SEMI M59 — Terminology for Silicon Technology

SEMI MF1392 — Test Method for Determining Net Carrier Density Profiles in Silicon Wafers by Capacitance-Voltage Measurements with a Mercury Probe

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