SEMI MF1049 - Practice for Shallow Etch Pit Detection on Silicon Wafers -

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Volume(s): Silicon Materials & Process Control
Language: English
Type: Single Standards Download (.pdf)
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Revision: SEMI MF1049-0308 (Reapproved 1018) - Current



High levels of etch pits are reported to indicate metallic contamination that is detrimental to wafer processing. This can be deduced from the density of etch pits on the surface of the wafer.


This Practice is used to detect shallow etch pits that may be related to the level of metallic impurities near the surface of silicon epitaxial or polished wafers.


This Practice covers detection of high densities of shallow etch pits on silicon wafers doped either p- or n-type and with resistivities as low as 0.005 Ω× cm. This Practice is applicable for silicon wafers cut from crystals grown in either a (111) or (100) crystal orientation.


This Practice is not recommended for use in defect density evaluations, but as a subjective means of estimating defect densities and distributions on the surface of a polished or epitaxial wafer.


This Practice utilizes a thermal oxidation process followed by a chemical preferential etchant to create and then delineate shallow etch pits.


Referenced SEMI Standards

SEMI C28 — Specification and Guide for Hydrofluoric Acid
SEMI C54 — Specification for Oxygen
SEMI C59 — Specification for Nitrogen
SEMI M17 — Guide for a Universal Wafer Grid
SEMI M59 — Terminology for Silicon Technology
SEMI MF1726 — Practice for Analysis of Crystallographic Perfection of Silicon Wafers
SEMI MF1727 — Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers
SEMI MF1809 — Guide for Selection and Use of Etching Solutions to Delineate Structural Defects in Silicon
SEMI MF1810 — Test Method for Counting Preferentially Etched or Decorated Surface Defects in Silicon Wafers

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