- SEMI MF1152 - Test Method for Dimensions of Notches on Silicon Wafers

Volume(s): Silicon Materials & Process Control
Language: English
Type: Single Standards Download (.pdf)
Abstract

This Standard was technically approved by the Silicon Wafer Global Technical Committee. This edition was approved for publication by the global Audits and Reviews Subcommittee on February 1, 2016. Available at www.semiviews.org and www.semi.org in March 2016; originally published by ASTM International as ASTM F1152-88; previously published February 2011.

 

Wafers must be accurately aligned in various processing equipment during integrated circuit manufacture.

 

A notch ground into the edge of the wafer at a specified orientation provides a positive method for such alignment. The accuracy of the critical dimensions of the notch controls the possible accuracy of the alignment.

 

This Test Method may be used for process control, quality control, and incoming or outgoing inspection.

 

Until an index of precision is determined based on an interlaboratory evaluation, this Test Method is not recommended for use in decisions between purchasers and suppliers.

 

This Test Method covers a nondestructive procedure to determine whether or not the dimensions, except for the blend radius, of fiducial notches on silicon wafers fall within specified limits.

 

This Test Method is specifically directed to the notch dimensions specified in SEMI M1, but with suitable modifications, the principles of this test method may be applied to any desired notch dimensions.

 

No test is provided for the blend radius at the apex of the notch.

 

The values stated in SI units are to be regarded as the standard. The values given in parentheses are for information only.

 

Referenced SEMI Standards

SEMI M1 — Specification for Polished Single Crystal Silicon Wafers

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