- SEMI MF1153 - Test Method for Characterization of Metal-Oxide Silicon (MOS) Structures by Capacitance-Voltage Measurements
This Standard was technically approved by the Silicon Wafer Global Technical Committee. This edition was approved for publication by the global Audits and Reviews Subcommittee on August 31, 2015. Available at www.semiviews.org and www.semi.org in October 2015; originally published by ASTM International as ASTM F1153-88; previously published November 2010.
Net carrier density present near the silicon-oxide interface may constitute an important acceptance requirement. Where there is not significant compensation by impurities of the opposite conductivity type, the material resistivity may be determined from this carrier density using SEMI MF723.
Flatband voltage is an important parameter in the manufacture of MOS devices. Its value is dependent on the work function difference between the silicon and the metal field plate, interface trapped charge, and fixed or trapped charge distributed within the oxide. It can be an indicator of anomalies in these values.
Instability of the flatband voltage of an MOS structure subjected to voltage stress at elevated temperatures is a measure of the mobile ionic charge density within the oxide. Most device applications require that mobile ionic charge be minimized.
The presence of unwanted subsurface p-n junctions may have deleterious effects on device operation.
This Test Method may be employed for qualification of furnaces or other semiconductor device-processing equipment where such qualification depends on the determination of contamination resulting from high mobile ionic charge density.
This Test Method covers measurement of metal-oxide-silicon (MOS) structures for flatband capacitance, flatband voltage, average carrier density within a depletion length of the semiconductor-oxide interface, displacement of flatband voltage after application of voltage stress at elevated temperatures, mobile ionic charge contamination, and total fixed charge density. Also covered is a procedure for detecting the presence of p-n junctions in the subsurface region of bulk or epitaxial silicon.
This Test Method is applicable to n-type and p-type bulk silicon with carrier density from 5 × 1014 to 5 × 1016 carriers per cm3, inclusive, and n/n+ and p/p+ epitaxial silicon with the same range of carrier density.
This Test Method is applicable for test specimens with oxide thicknesses of 50 to 300 nm.
This Test Method can give an indication of the density of defects within the MOS structure. These defects include interface trapped charge, fixed oxide charge, trapped oxide charge, and permanent inversion layers.
This Test Method is applicable for measurement of mobile ionic charge density of 1 × 1010 cm−2 or greater. Alternative techniques, such as the triangular voltage sweep method, may be required where mobile ionic charge density less than 1 × 1010 cm−2 must be measured.
This Test Method is applicable for measurement of total fixed charge density of 5 × 1010 cm−2 or greater. Alternative techniques, such as the conductance method, may be required where the interface trapped-charge density component of total fixed charge of less than 5 × 1010 cm−2 must be measured.
Referenced SEMI Standards
SEMI M59 — Terminology for Silicon Technology
SEMI MF576 — Test Method for Measurement of Insulator Thickness and Refractive Index on Silicon Substrates by Ellipsometry
SEMI MF723 — Practice for Conversion Between Resistivity and Dopant or Carrier Density for Boron-Doped, Phosphorus-Doped, and Arsenic-Doped Silicon