- SEMI MF1726 - Practice for Analysis of Crystallographic Perfection of Silicon Wafers
This Standard was technically approved by the Silicon Wafer Global Technical Committee. This edition was approved for publication by the global Audits and Reviews Subcommittee on August 31, 2015. Available at www.semiviews.org and www.semi.org in November 2015; originally published by ASTM International as ASTM F1796-97; previously published November 2010.
The use of silicon crystals in many semiconductor devices requires a consistent atomic lattice structure. Crystal defects disturb local lattice energy conditions that are the basis for semiconductor behavior. These defects have distinct effects on essential semiconductor-device manufacturing processes such as alloying and diffusion.
Epitaxial growth processes are used extensively in the manufacture of silicon electronic devices. Stacking faults introduced during epitaxial growth can cause ‘soft’ electrical characteristics and preferential micro plasma breakdowns in diodes.
Epitaxial defects are more clearly delineated with the use of this destructive etching procedure. Epitaxial wafers may however be classified nondestructively by this method without the destructive preferential etching and inspection steps.
This Practice provides guidance regarding procedures for analysis of crystal defects of silicon ingots from which silicon wafers are cut.
This Practice, together with the referenced standards, may be used for process control, research and development, and material acceptance purposes.
This Practice covers the determination of the density of crystallographic defects in unpatterned polished and epitaxial silicon wafers. Epitaxial silicon wafers may exhibit dislocations, hillocks, shallow pits or epitaxial stacking faults, while polished wafers may exhibit several forms of crystallographic defects or surface damage. Use of this Practice is based upon the application of several referenced standards in a prescribed sequence to reveal and count microscopic defects or structures.
This Practice is suitable for use with epitaxial or polished wafers grown in either  or  direction and doped either p- or n-type with resistivity greater than 0.005 Ω·cm.
This Practice is suitable for use with epitaxial wafers with layer thickness greater than 0.5 µm.
Additional requirements on the material to be tested are listed in SEMI MF1810.
Referenced SEMI Standards
SEMI M59 — Terminology for Silicon Technology
SEMI MF95 — Test Method for Thickness of Lightly Doped Silicon Epitaxial Layers on Heavily Doped Silicon Substrates Using an Infrared Dispersive Spectrophotometer
SEMI MF523 — Practice for Unaided Visual Inspection of Polished Silicon Wafers Surfaces
SEMI MF1809 — Guide for Selection and Use of Etching Solutions to Delineate Structural Defects in Silicon
SEMI MF1810 — Test Method for Counting Preferentially Etched or Decorated Surface Defects in Silicon Wafers