- SEMI MF1771 - Test Method for Evaluating Gate Oxide Integrity by Voltage Ramp Technique

Volume(s): Silicon Materials & Process Control
Language: English
Type: Single Standards Download (.pdf)

This Standard was technically approved by the Silicon Wafer Global Technical Committee. This edition was approved for publication by the global Audits and Reviews Subcommittee on February 1, 2016. Available at www.semiviews.org and www.semi.org in April 2016; originally published by ASTM International as ASTM F1771-97; previously published November 2010.


The technique outlined in this Test Method is meant to standardize the procedure, analysis and reporting of oxide integrity data via the voltage ramp technique among interested parties. However, since the values obtained cannot be entirely divorced from the process of fabricating the test structure, suitable correlations should be performed based on process needs and structure selection. This correlation should include sample size as well as device geometry.


Measurement of the electrical integrity of oxides grown on silicon wafers may also be used in-house as a means of monitoring the quality of furnaces and other processing steps as well as judging the impact of changing some processing steps.


Selection of various edge and area intensive structures is crucial for isolating the nature of the defects. Techniques for using such structures to isolate the nature of detected defects is beyond the scope of this Test Method.


The actual results are somewhat dependent on the choice of gate electrode. Polysilicon gates have the advantage of being identical to finished product in many instances. Even for polysilicon gates, exact results depend upon values chosen for polysilicon thickness, doping, and sheet resistance.


The techniques outlined in this Standard are for the purpose of standardizing the procedure of measurement, analysis, and reporting of oxide integrity data between interested parties.


This Test Method makes no representation regarding actual device failure rates or acceptance/rejection criteria.


While some suggestions for data analysis are included in later sections of this Test Method, interpretation of results is beyond the scope of this Standard. Any such interpretations should be agreed upon between interested parties prior to testing. For example, a variety of failure criteria are included to permit separation of so-called intrinsic and extrinsic oxide failures.


The background of this Test Method is provided in Related Information 1.


This Test Method covers the procedure for gauging the electrical strength of silicon dioxide thin films with thicknesses ranging from approximately 3 to 50 nm. In the analysis of films of 4 nm or less, the impact of direct tunneling on the current-voltage characteristics, and hence the specified failure criteria defined in ¶ 2.5, must be taken into account. Since oxide integrity strongly depends on wafer defects, contamination, cleanliness, as well as processing, the users of this Test Method are expected to include wafer manufacturers and device manufacturers.


Referenced SEMI Standards

SEMI M51 — Test Method for Characterizing Silicon Wafers by Gate Oxide Integrity
SEMI M59 — Terminology for Silicon Technology

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