VLSI - ASIC Design Flow Overview

In this course, we will learn the complete ASIC design flow, covering the key stages required to transform a concept into a manufacturable chip. The course begins with specification, followed by architecture and RTL design, focusing on system organization and hardware implementation. We then explore functional verification and gate-level simulation to ensure design correctness. The course also covers Design for Testability (DFT), Static Timing Analysis (STA), and introduces physical design, including layout and GDS-II generation, providing a clear view of the overall VLSI design flow. 
 

This is a self-paced eLearning module with structured content, and knowledge checks. You are expected to complete all the sections to earn the completion credits. 

Course Objectives

• Define the key stages involved in the complete ASIC design flow.
• Explain the transitions from specification to architecture and RTL design.
• Describe the role of functional verification and gate-level simulation in ensuring design correctness. 
• Understand the importance of DFT and STA in achieving testability and timing closure.
• Identify the major steps in physical design including design, including layout and GDS-II generation. 

Course Duration

60 Minutes

Target Audience

Entry level engineers, technicians, students or any individuals working directly in the semiconductor industry